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REV. 0
AD1833A
–14–
I
2
S Timing
I
2
S timing uses an
L
/RCLK to define when the data being trans-
mitted is for the left channel and when it is for the right channel.
The
L
/RCLK is low for the left channel and high for the right
channel. A bit clock running at 64 f
S
is used to clock in the data.
There is a delay of 1 bit clock from the time the
L
/RCLK signal
changes state to the first bit of data on the SDINx lines. The data
is written MSB first and is valid on the rising edge of the bit clock.
Left-Justified Timing
Left-justified (LJ) timing uses an L/
R
CLK to define when the
data being transmitted is for the left channel and when it is for
the right channel. The L/
R
CLK is high for the left channel and
low for the right channel. A bit clock running at 64 f
S
is used
LEFT CHANNEL
RIGHT CHANNEL
+1
LSB
MSB
L
/RCLK
INPUT
BCLK
INPUT
SDATA
INPUT
+2
–2
–1
MSB
+1
LSB
+2
–2
–1
MSB
Figure 6. I
2
S Timing Diagram
LEFT CHANNEL
RIGHT CHANNEL
+1
LSB
L/RCLK
INPUT
BCLK
INPUT
SDATA
INPUT
+2
–2
–1
MSB
+1
LSB
+2
–2
–1
MSB
–1
MSB
Figure 7. Left-Justified Timing Diagram
LEFT CHANNEL
RIGHT CHANNEL
+1
LSB
L/
R
CLK
INPUT
BCLK
INPUT
SDATA
INPUT
+2
–2
–1
LSB
MSB
+1
LSB
+2
–2
–1
MSB
Figure 8. Right-Justified Timing Diagram
to clock in the data. The first bit of data appears on the SDINx
lines when the L/
R
CLK toggles. The data is written MSB first
and is valid on the rising edge of the bit clock.
Right-Justified Timing
Right-justified (RJ) timing uses an L/
R
CLK to define when the
data being transmitted is for the left channel and when it is for
the right channel. The L/
R
CLK is high for the left channel and
low for the right channel. A bit clock running at 64 f
S
is used
to clock in the data. The first bit of data appears on the SDINx
8-bit clock periods (for 24-bit data) after L/
R
CLK toggles. In RJ
mode, the LSB of data is always clocked by the last bit clock
before L/
R
CLK transitions. The data is written MSB first and is
valid on the rising edge of the bit clock.
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